The invention is directed to an improved approach for designing, testing, and manufacturing integrated circuits.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may uses a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist.
Based upon this geometric information, photomasks are created for lithographic manufacturing of the electronic product. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. A typical photolithography system projects UV light energy on to and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer.
Other processes may also occur during the process of manufacturing an intenerated circuit. For example, etching, Electroplated copper deposition (ECD), and chemical mechanical polishing (CMP) may be used to form interconnects for the IC. The lithographic patterns define the dimensions of the circuitry that is transferred to a silicon wafer, with the patterns subsequently used with the etch process to physically etch the features into the wafer surface or other thin films deposited on the wafer surface. Etch equipment includes mechanisms to selectively remove materials (e.g. oxide) from a wafer surface or thin films on the wafer surface patterned with lithography equipment. ECD is a process step in a copper damascene flow that is used to deposit copper material within the interconnect structures.
However, significant variations may arise during the process of manufacturing the IC. For example, lithography mask creation and printing assume that projection is done on a film, within a predetermined depth of focus range. However pattern dependencies between the process by which the ICs are fabricated and the pattern that is being created often cause processed films to have significant variation in thickness across a surface, resulting in variation in feature dimensions (e.g. line widths) of ICs that are patterned using the mask.
In addition, the variation in thickness may cause sloping or curved surfaces to appear. These sloped or curved surfaces may result in reflected light during the lithography process. The reflected light may result in process variations that are not accounted for by existing or conventional process models.
Moreover, the projected light will be absorbed and transmitted through the resist. The propagation of light through the resist will influence spatial variation between the top and bottom of the exposed resist layer and may influence the resulting shape of the printed feature. The light may also reflect off an underlying material and toward the top surface of the photoresist inducing variation in the resulting feature shape as well. Variation in underlying material thickness may influence how the light propagates through the resist as well.
The present invention is directed to a method, system, and computer program product for modeling and correcting for the effects of such reflections during lithography processing. Other and additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.